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Filling the Gap Between Digital and Analog Verification, Parts 1 and 2 and Q&A

by Henry Chang, Vice President and Ken Kundert, President
The Q&A panel will also include Simul Barua, Technical Lead, Design Verification, Ulkasemi, Inc., and Jonathan David, Analog and Mixed-Signal Chip Verification Consultant

Analog models play a critical role in a full chip verification flow. Most SoCs today include analog circuitry, and the industry has struggled to find an effective and consistent methodology and process for comprehensively verifying the functionality of this integrated digital logic and analog circuitry. Even chips that are considered digital have analog blocks such as power regulators, phase locked loops, and serial deserializer. Whether teams use a digital-on-top flow with analog released as IP to the digital team, or an analog-on-top flow, the presence of complicated digital and analog is unlikely to work as planned unless fully verified. If first pass functional silicon is the goal, a full chip verification flow that includes the analog is required to truly cover 100% of the functionality.

This presentation will discuss what it takes to be successful in modeling analog in a full chip digitally-driven verification flow. It will cover what needs to be modeled, and more importantly, will discuss how the models need to be validated against the analog schematics. It will also discuss some of the organizational changes that need to be addressed in order for full chip verification with analog to become a reality.

The talk is intended for anyone doing verification (digital, analog, mixed-signal) and anyone creating analog models and doing analog model validation (model vs. schematic checking).

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Part 1: October 17, 2024

0:00:00 Introductions 0:04:37 Goal / causes of Respins 0:10:13 Verification gap 0:16:35 The need for abstraction 0:25:06 Model types 0:31:18 Starting from an analog specification

0:40:02 Model validation: model vs. schematics              (MVS) 0:43:47 Analog verification 0:46:50 State of the Industry 0:52:42 Closing the Gap 1:00:17 Q&A

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Part 2: October 24, 2024 Getting to 4 hours per validated model for the lifecycle of the model

0:00:00 Introductions 0:01:57 Getting to 4 Hours 0:05:31 Modeling validation (MVS) 0:07:29 Practical analog verification 0:13:27 Specification driven verification 0:15:37 Models in Minutes (MiM) 0:23:07 AV utility 0:25:39 Work flows 0:27:47 Demo 1: Web flow, Verilog-AMS model,              basic tests, tolerance checking

0:36:40 Demo 2: Symbol import, command line              flow (no web), text specifications,              SystemVerilog model 0:44:51 Demo 3: Algorithmic circuit, state              variables, testbench macros 0:49:51 Demo 4: State variables, testbench              macros 0:55:48 Demo 3: Delta-sigma waveform 1:00:40 Our products and services along with              special offers 1:03:43 Q&A

Please be sure to watch our short segment on our products and services (click on link and then press play) and on our special offers for this webinar.
Please complete our interest survey or contact us if you have interest in MiM, our analog verification class, analog modeling and verification services, or consulting.

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Part 3: November 14, 2024 Top 1 or 2 considerations when embarking on analog verification and modeling and Q&A

00:00:00	Welcome
00:01:29	Analog verification is straightforward (getting started operationally and technically)
00:07:38	Analog verification flow and where the roadblocks are
00:14:38	Choosing the right approach for analog modeling
00:29:14	How to quickly ramp up to having all of the components needed in a verification environment
00:37:48	Q&A
00:38:02	Does the same person develop both the analog model and testbench? If so, what is the best way to prevent any bias during this process?
00:41:49	How much time or effort does it take to development analog models and testbenches?
00:42:50	Can people with digital domain expertise develop analog models too? If so, what are the challenges they might face when developing analog models?
00:44:53	What does an ideal analog verification team look like? How many people on the team? What skills do they need?
00:48:22	What needs to be placed in an analog model to make them complete?
00:51:32	How do we decide on the model boundary for the analog block? Is it better to model at a lower level or higher level? Does this answer change when using MiM?
00:56:35	How often should model vs. schematic (MVS) checking be done for the models?
00:57:22	Can the digital verification engineer do this?
00:59:22	What is the best way to train to become an analog modeling and verification engineer? And how long will it take for someone to become proficient at analog modeling and verification?
01:02:33	Do teams using a mixed-signal verification flow use schematics, and how do do they achieve coverage for their mixed-signal designs? Which is more preferred for analog verification: the analog models or schematics?
01:04:43	Is there a time when I might need both Verilog-AMS and System Verilog models?
01:06:48	Is there a performance difference between Verilog-AMS wreal and SystemVerilog real?
01:09:04	When is it important to use SystemVerilog discrete electrical models instead of SystemVerilog real models?
01:11:21	How do I add environmental effects such as temperature (or safety) to analog models?

Links from the webinar:

• The link to the pre-webinar survey
• Our website
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• The DVCon24 videos mentioned in the video can be found here
• Our email contact is info@designers-guide.com