Upcoming Webinars:

• A Q&A session on analog modeling and verification on Thursday, November 14 from 04:00 (UTC) to 05:00 (UTC). For details, please click here. The registration code is "INEEDAV". 

Past Webinars:

Filling the Gap Between Digital and Analog Verification, Parts 1 and 2

by Henry Chang, Vice President and Ken Kundert, President
The Q&A panel will also include Simul Barua, Technical Lead, Design Verification, Ulkasemi, Inc., and Jonathan David, Analog and Mixed-Signal Chip Verification Consultant

Analog models play a critical role in a full chip verification flow. Most SoCs today include analog circuitry, and the industry has struggled to find an effective and consistent methodology and process for comprehensively verifying the functionality of this integrated digital logic and analog circuitry. Even chips that are considered digital have analog blocks such as power regulators, phase locked loops, and serial deserializer. Whether teams use a digital-on-top flow with analog released as IP to the digital team, or an analog-on-top flow, the presence of complicated digital and analog is unlikely to work as planned unless fully verified. If first pass functional silicon is the goal, a full chip verification flow that includes the analog is required to truly cover 100% of the functionality.

This presentation will discuss what it takes to be successful in modeling analog in a full chip digitally-driven verification flow. It will cover what needs to be modeled, and more importantly, will discuss how the models need to be validated against the analog schematics. It will also discuss some of the organizational changes that need to be addressed in order for full chip verification with analog to become a reality.

The talk is intended for anyone doing verification (digital, analog, mixed-signal) and anyone creating analog models and doing analog model validation (model vs. schematic checking).

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Part 1: October 17, 2024

0:00:00 Introductions 0:04:37 Goal / causes of Respins 0:10:13 Verification gap 0:16:35 The need for abstraction 0:25:06 Model types 0:31:18 Starting from an analog specification

0:40:02 Model validation: model vs. schematics              (MVS) 0:43:47 Analog verification 0:46:50 State of the Industry 0:52:42 Closing the Gap 1:00:17 Q&A

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Part 2: October 24, 2024 Getting to 4 hours per validated model for the lifecycle of the model

0:00:00 Introductions 0:01:57 Getting to 4 Hours 0:05:31 Modeling validation (MVS) 0:07:29 Practical analog verification 0:13:27 Specification driven verification 0:15:37 Models in Minutes (MiM) 0:23:07 AV utility 0:25:39 Work flows 0:27:47 Demo 1: Web flow, Verilog-AMS model,              basic tests, tolerance checking

0:36:40 Demo 2: Symbol import, command line              flow (no web), text specifications,              SystemVerilog model 0:44:51 Demo 3: Algorithmic circuit, state              variables, testbench macros 0:49:51 Demo 4: State variables, testbench              macros 0:55:48 Demo 3: Delta-sigma waveform 1:00:40 Our products and services along with              special offers 1:03:43 Q&A

Please be sure to watch our short segment on our products and services (click on link and then press play) and on our special offers for this webinar.
Please complete our interest survey or contact us if you have interest in MiM, our analog verification class, analog modeling and verification services, or consulting.

Links from the webinar:

• The link to the pre-webinar survey
• Our website
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• Subscribe to our Youtube channel
• The DVCon24 videos mentioned in the video can be found here
• Our email contact is info@designers-guide.com