Analog and Mixed-Signal Verification (hybrid)

This challenging course provides participants with the tools they need to take on the task of verifying complex analog, RF, and mixed-signal integrated circuits. It combines lecture with a substantial amount of time in the lab to teach the overall analog verification process. You will learn how to develop a verification plan, functional models of analog blocks, regression tests for those models, and a fully verified Verilog model for the entire analog portion of the design for use in chip-level verification. Considerable time is spent on best practices that allow you to avoid the common pitfalls and user-traps common to analog verification.

Target Audience

The class is intended for anyone who would benefit from a working knowledge of analog verification or from improving their skills with Verilog-A/MS. These include: analog verification engineers, analog designers, analog design leads, and digital verification engineers and CAD engineers who meet the prerequisites.

Course Contents

• Day 1: Introduction and Block-Level Analog Modeling
• Day 2: Block-Level Mixed-Signal Modeling
• Day 3: Block Level Analog Verification
• Day 4: System Level Analog Verification
• Day 5: Taking Analog Verification Into Production

Please see our onsite "Analog and Mixed-Signal Verification (4-5 days)" class for the details on the prerequisites, course contents, and requirements. Although we follow the same five day format as the five day onsite class, you will have access to the class for one year and can take the class over a one year period however you like.

Availability

Anytime. The class is offered in hybrid fashion. Please contact us for details and to sign up.

Pricing

Please contact us

Included in the Online Version

• Online access to the class videos for a year
• Downloadable version of the class slides for your personal use
• For those interested, access to the class version of our on-line model and MVS (model vs. schematic) testbench generator¹ for two months

Analog and Mixed-Signal Verification (4-5 days)

This challenging four or five day course provides participants with the tools they need to take on the task of verifying complex analog, RF, and mixed-signal integrated circuits. It combines lecture with a substantial amount of time in the lab to teach the overall analog verification process. You will learn how to develop a verification plan, functional models of analog blocks, regression tests for those models, and a fully verified Verilog model for the entire analog portion of the design for use in chip-level verification. Considerable time is spent on best practices that allow you to avoid the common pitfalls and user-traps common to analog verification.

Target Audience

The class is intended for anyone who would benefit from a working knowledge of analog verification or from improving their skills with Verilog-A/MS. These include: analog verification engineers, analog designers, analog design leads, and digital verification engineers and CAD engineers who meet the prerequisites.

Instructors

Ken Kundert and Henry Chang

Prerequisites

Though not required, it is helpful if students have a working knowledge of Verilog-A, analog circuits and their design, and the Cadence design environment. The better prepared you are, the more you will get from the class.

Course Contents

Day 1 — Introduction and Block-Level Analog Modeling

• Introduction to analog verification
• Verification planning
• Verilog-A basics
• Analog block-level functional modeling
• Labs exercises

Day 2 — Block-Level Mixed-Signal Modeling

• Verilog basics
• Verilog-AMS basics
• Mixed-signal block-level functional modeling
• Mixed-signal netlists (connect modules)
• Assertions
• Labs exercises

Day 3 — Block Level Analog Verification

• Block-level verification strategy
• Writing self-checking regression tests
• Techniques for testing common mixed-signal blocks
• Overcoming analog verification problems
• Labs exercises

Day 4 — System Level Analog Verification

• System-level verification strategy
• Verilog modeling of analog systems
• Verifying the top-level model
• Chip-level verification strategy
• Verification review
• Labs exercises

Day 5 (optional) — Taking Analog Verification Into Production

• Specification-driven verification
• Generating models with Models-in-Minutes
• Generating MVS (model vs. schematic) testbenches with Models-in-Minutes
• Verification from the Linux command line
• Best analog verification practices in a production setting
• Labs exercises

Days 1 & 2 teaches the basics of Verilog, Verilog-A and Verilog-AMS, with an emphasis on best practices. Day 3 is often overlooked, but it is perhaps the most important day. It is where we teach you to create automated regression tests that thoroughly exercise and verify mixed-signal designs. It is a very unique aspect of this class. On day 4 we cover chip/analog subsystem level connectivity, function checking, and how to write Verilog models for chip level verification, with a focus on not only how to make them very efficient, but also how to assure that they are functionally equivalent to the circuit.

The class is structured to alternate between lecture and labs, with a large percentage of the class dedicated to rather open ended labs. In this way, everyone is challenged and learns a great deal, regardless of their experience level. People that are new to Verilog-AMS often just use the labs to gain experience with the language and simulator. Those with a lot of experience with the language challenge themselves more with the verification aspects.

Requirements

Access to a Verilog-A, Verilog-AMS, and SystemVerilog simulator. If you want to be able to use our lab materials, then you'll need access to the Cadence tools: Schematic capture, ADE or Maestro, AMS Designer, Hierarchy Editor, and Simvision. Please contact us if you need more details.

Availability

Available. Please contact us for scheduling.

Pricing

Please contact us

Modeling Basics for Analog/Mixed-Signal/RF Design and Verification (3 days)

For good reasons, modeling has become an integral part of analog design, especially as design complexity increases. Most designers have never taken a deep class in Verilog-A where what the model is doing is tied with the underlying simulator. As a result, designers often write models that simulate slowly, fail to produce desired results, and have convergence and time step issues. This class teaches the Verilog-A and Verilog-AMS languages with an emphasis on creating well formulated models that run efficiently and do not suffer from convergence or simulation issues. The goal of this class is to give a solid foundation to engineers new to modeling and to improve the modeling skills of designers already familiar with modeling.

Target Audience

The class is intended for anyone who would benefit from having a solid foundation in Verilog-A and Verilog-AMS. These include: Analog/Mixed-Signal/RF Designers, Novice Analog or Mixed-Signal Verification Engineers, EDA Engineers.

Instructors

Ken Kundert and Henry Chang

Prerequisites

Though not required, ithelpful if students have a working knowledge analog circuits and their design, and the Cadence design environment. The better prepared you are, the more you will get from the class.

Learning Objectives

• Learn the fundamentals of the Verilog-A and Verilog-AMS languages
• Learn enough Verilog (digital) to write good Verilog-AMS for the digital portions of the model
• Learn the fundamentals of what makes a good model
• Learn how what you write ties in with the simulator in terms of accuracy, robustness, and efficiency
• Learn best practices of modeling
• Uses challenging lab exercises to reinforce learning
• Gain a solid foundation of modeling to get more out of the Analog Design Verification class
• Be able to get questions around analog modeling answered; questions which may be beyond the scope of the class

Course Contents

• Introduction
• Device Modeling with Verilog-A
• Functional Modeling with Verilog-A
• Verilog-A Best Practices
• Modeling with Verilog
• Modeling with Verilog-AMS
• Modeling with Verilog-AMS wreals
• Power Domains and Connect Modules
• Introduction to testbench writing

Requirements

Access to a Verilog-A, Verilog-AMS, and SystemVerilog simulator. If you want to be able to use our lab materials, then you'll need access to the Cadence tools: Schematic capture, ADE or Maestro, AMS Designer, Hierarchy Editor, and Simvision. Please contact us if you need more details.

Availability

Available. Please contact us for scheduling.

Pricing

Please contact us

Effective Use of Circuit Simulation for Analog/Mixed-Signal/RF Designs (3 days)

The emphasis of this class is on increasing the designer's effectiveness when using a simulator by giving them a basic understanding of how the simulator works so that they can better control it and resolve problems that come up and by exposing them to many simulation best practices. From the class, the designer should be able to better discern when simulation results are good predictors of actual performance and when simulators have limitations. Throughout the class, different circuit examples from different design domains are given. The labs focus on setting up testbenches to reinforce the topics being taught.

Target Audience

The class is intended for analog/mixed-signal/RF designers, and analog verification engineers.

Instructors

Ken Kundert

Course Contents

• When to simulate
• How the simulator works
• Formulating and solving the equations
• Tolerances
• DC analysis
• Small-signal analysis (including AC, XF, noise, stability/loop gain, etc.)
• Transient analysis
• Fourier analysis
• Corner Analysis and Monte Carlo Simulation
• Introduction to RF simulation

Availability

Available. Please contact us for scheduling.

Pricing

Please contact us