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Webinar Registration Request
As System-on-Chip (SoC) designs become increasingly intricate, the intricacies of analog and digital circuitry present substantial verification challenges. Traditional chip-level verification processes often prioritize digital functionality, neglecting critical aspects of the analog portion under the presumption of correctness. This webinar delves into integrating analog models into the testbench environment, demonstrating how this approach can enhance the comprehensive verification of SoCs. We will explore various analog modeling methodologies and their integration into a UVM-based full-chip verification testbench. Through this analysis, we will evaluate the performance and impact of these approaches on overall verification efficiency. We will have a Q&A panel following the talk where we'll entertain questions on the talk and on verification in general. If you are interested in attending this webinar, please register below. Prior to the event, we will send out a link for the webinar to the email address submitted to as many people as we can.2 To submit a registration request, please enter the following information: *Required 1If you do not have a company or university email address and would like to attend, or if you have any questions or comments, please contact us. Please see our privacy policy to understand how we protect and use your data. 2Due to our video conferencing provider, we are limited in the number we can have at our webinar. If we find we have enough people for a second session, we will consider hosting one. |
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