Webinar Registration Request

Filling the Gap Between Digital and Analog Verification

by Henry Chang, Vice President and Ken Kundert, President
The Q&A panel will also include Simul Barua, Technical Lead, Design Verification, Ulkasemi, Inc., and Jonathan David, Analog and Mixed-Signal Chip Verification Consultant

Analog models play a critical role in a full chip verification flow. Most SoCs today include analog circuitry, and the industry has struggled to find an effective and consistent methodology and process for comprehensively verifying the functionality of this integrated digital logic and analog circuitry. Even chips that are considered digital have analog blocks such as power regulators, phase locked loops, and serial deserializer. Whether teams use a digital-on-top flow with analog released as IP to the digital team, or an analog-on-top flow, the presence of complicated digital and analog is unlikely to work as planned unless fully verified. If first pass functional silicon is the goal, a full chip verification flow that includes the analog is required to truly cover 100% of the functionality.

This presentation will discuss what it takes to be successful in modeling analog in a full chip digitally-driven verification flow. It will cover what needs to be modeled, and more importantly, will discuss how the models need to be validated against the analog schematics. It will also discuss some of the organizational changes that need to be addressed in order for full chip verification with analog to become a reality.

The talk is intended for anyone doing verification (digital, analog, mixed-signal) and anyone creating analog models and doing analog model validation (model vs. schematic checking).

Due to our video conferencing provider, we are limited in the number we can have at our webinar. Prior to the event, we will send out a link for the webinar to the email address submitted to as many people as we can. If we find we have enough people for a second session, we will consider hosting one. To submit a registration request, please enter the following information:

Event:	Webinar
Title:	Filling the Gap Between Digital and Analog Verification
Date:	Part 1: October 17, 2024; Part 2: October 24, 2024
Time:	10:00am to 11:30am (PDT)
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