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What’s New

We are co-authors on two DVCon 2024 papers on AMS and UVM. The first is "Advanced UVM Based Chip Verification Methodology With Full Analog Functionality," which was co-authored with Simul Barua and BNU Farshad of Ulkasemi, Inc.. The second is "UVM Testbench Automation for AMS Designs," in which Jonathan David of Innophase Inc. is the lead author. Here's a link to the videos and the PDFs of the presentations and papers.

The next generation of Models in Minutes (MiM-2) is available and has been in production use by our early adopters for several months. The key features of MiM-2 can be found at the end of our Products page. MiM-2 fully supports SystemVerilog with discrete electrical ports using SystemVerilog UDTs (User Defined Types).

Read case studies and customer testimonials on The Designer's Guide Advantage.

A systematic analog verification methodology is a huge differentiator in the design of today’s complex consumer electronic ICs.

Summit Lake, near Agnew Pass on the Pacific Crest Trail

Analog Verification

Analog verification, mixed-signal verification, AMS verification, DMS verification; many names for essentially the same thing: a process to assure that complex analog and mixed-signal systems work as expected when fabricated.

Digital verification follows a process that is highly refined and heavily automated. The same cannot be said of most analog verification. Whereas digital verification is systematic and deliberate, analog verification tends toward being ad hoc and opportunistic. With the lack of synthesis in analog design it is essential to verify that the modeled functionality matches that of the corresponding schematic. Most people settle for writing models by hand, which is slow and tedious. They validate these models using existing schematic-based testbenches. Such testbenches are primarily designed to verify performance rather than function. They generally test only one mode and one setting, leaving all other modes and settings untested. This approach is expensive and fails to find many errors in both the models and the schematics. As such, errors that could easily be caught early do not get found until the chip is fabricated.

Designer’s Guide

We appreciate the support Designer’s Guide provides with the tools. Because of their deep knowledge of verification, simulation, and modeling best practices, they’ve been able to help us make strategic decisions in verification, and help us debug a variety of accuracy and efficiency issues.
Lead verification engineer on a communications chip

Our company provides products that automate the analog verification process, making it much more efficient and effective. Specifically, our products are used to automate the creation and validation of block-level models of the analog section. Once validated, these models form the foundation for system- and chip-level verification. Our tools support both SystemVerilog and Verilog-AMS analog verification flows.

If you are new to analog verification, we also offer consulting, training, and services to help you get started.


Models in Minutes, or MiM, accepts a simple functional spec sheet for individual blocks and generates a complete model of the block and an exhaustive fully autonomous testbench that validates the model against its schematic. Autonomous testbenches test every mode and setting of the model and give a simple pass/fail result without the need to examine a single waveform. They also test the assertions to assure that they will alert you to missing or invalid supplies and bias currents during system-level simulations.

Model Validation

MiM has the only automated model vs. schematic comparison tool on the market.
Lead verification engineer

People generally underestimate the value of fully validated models. Without validation, models often represent what was intended rather than what was implemented. The result: simulations with models show the expected behavior and hide actual problems in the design. In addition, the act of validating models against their schematics exposes problems in the design of individual blocks much earlier when they are easier to recover from. Our experience indicates that roughly half the bugs in a typical mixed-signal design are found during model validation.

Next Steps

Navigate through the tabs on the left and view our videos to explore our offerings and please contact us if you have questions or would like to get started.

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