Cascade Canyon, Grand Tetons National Park
Functional Verification Products
Designer’s Guide Consulting is offering a new technology that allows an analog designer or an analog verification engineer to create Verilog or Verilog-AMS functional models (with or without wreals) of their analog and mixed-signal circuits in minutes. These models are geared for analog and mixed-signal chip-level functional verification, and as such, facilitate the catching of errors in the following areas of your chip:
the analog, RF, or mixed-signal sections,
the analog-digital interface,
the portion of the digital section that talks to the analog, and
the embedded software that talks to the analog.
Not only is it easy and fast to create these models (10-50x faster than writing models by hand), but we validate that the models created functionally match your schematics. Validated models move you from the realm of faith-based verification to true verification. Furthermore, the models created capture our extensive modeling experience and are optimized based on a detailed knowledge of the internal workings of the simulator, and so are always both efficient and robust.
Currently, 70%-80% of the analog verification and mixed-signal chip-level verification effort is devoted to creating models for the analog blocks, and analog verification can consume 20% or more of the total analog design effort. Furthermore, engineers capable of performing analog verification are very difficult to find or develop. The lack of experienced analog verification engineers and their relatively low level of productivity limits the overall effectiveness of analog verification by limiting both the quality of the tests and the coverage of the testing.
The impact of all of these hurdles is greatly reduced with the use of our modeling technology. It dramatically accelerates the modeling and testing of the design and improves the quality of the testing at a very reasonable cost. It also allows you to develop a complete test suite for your design with a relatively small analog verification effort and have the resulting models and tests be of much higher quality and consistency than would otherwise be possible.
With our models you can finally perform true mixed-signal functional verification at the chip-level that is traceable to the transistor level.
Please contact us us for more details. We'd be happy to provide you with a detailed brochure, give you access to our demonstration videos, and/or be happy to set up a meeting with you to give a presentation and demonstration of this technology. We also have a streamlined evaluation mechanism with on-line tutorials and extensive on-line documentation.
Synthesizer Noise and Jitter Analyzer
Quickly predict the phase noise or jitter of a wide variety of PLL architectures used for frequency syntheses and clock distribution. This phase noise and jitter analyzer takes simple performance metrics for each of the blocks that make up the synthesizer and predicts the phase noise and jitter at the output of the synthesizer. It allows you to quickly explore trade-offs and understand how each of the design parameters contributes to the over all noise of the synthesizer. Please contact us for more information.
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