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The Grand Canyon

The following documents give an overview of the verification methodology we employ.

Introduction to Analog Verification

Presents the basic concepts of analog verification and show how it can be used to find a wide variety of functional errors in complex mixed-signal integrated circuits. Originally published in IEEE Solid-State Circuits Magazine in Fall 2009 under the title "Verifying all of an SOC — Analog Circuitry Included".

Read the full paper.

Top-Down Design and Verification of Mixed-Signal Circuits

Provides an extensive introduction and motivation for top-down verification. Top-down verification is a refinement of the top-down design methodology that adds considerable rigor and greatly reduces the chance of a functional failure. This brief overview was published in EE Times in June 2005.

Read the full paper.

Verification of Complex Analog Integrated Circuits

Functional complexity in analog, mixed-signal, and RF (A/RF) designs is increasing dramatically. Today’s simple A/RF functional block such as an RF receiver or power management unit can have hundreds to thousands of control bits. A/RF designs implement many modes of operation for different standards, power saving modes, and calibration. Increasingly, catastrophic failures in chips are due to functional bugs, and not due to missed performance specifications. Functionally verifying A/RF designs is a daunting task requiring a rigorous and systematic verification methodology. As occurred in digital design, analog verification is becoming a critical task that is distinct from design. This paper describes a verification methodology to address these challenges. Is is a more detailed look at the methodology that was published in the Proceedings of the IEEE in February 2007.

Read the full paper.

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More information can be found in the form of papers, books, discussion forum, etc., on the companion community website, Here are some that apply to issues in functional and performance verification.

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