Designer’s Guide Consulting
Designer’s Guide Consulting :: Analog Verification Designer’s Guide Consulting :: Analog Verification Designer’s Guide Consulting :: Analog Verification
Excellent class. Very challenging, but fun. I learned a huge amount.

Ruby Lake, Ansel Adams Wilderness

We offer training classes in analog simulation, modeling, and verification that are both demanding and rewarding.

Analog Verification (4-5 days)

This challenging four day course provides participants with the tools they need to take on the task of verifying complex analog, RF, and mixed-signal integrated circuits. It combines lecture with a substantial amount of time in the lab to teach the overall analog verification process. You will learn how to develop a verification plan, functional models of analog blocks, regression tests for those models, and a fully verified Verilog model for the entire analog portion of the design for use in chip-level verification.

Considerable time is spent on best practices that allow you to avoid the common pitfalls and user-traps common to analog verification.

Target Audience

The class is intended for anyone who would benefit from a working knowledge of analog verification or from improving their skills with Verilog-A/MS. These include: analog verification engineers, analog designers, analog design leads, and digital verification engineers and CAD engineers who meet the prerequisites.


Ken Kundert and Henry Chang.


Though not required, it is helpful if students have a working knowledge of Verilog-A, analog circuits and their design, and the Cadence design environment. The better prepared you are, the more you will get from the class.

Course Contents

Day 1 — Introduction and Block-Level Analog Modeling

  • Introduction to analog verification
  • Verification planning
  • Review of Verilog-A
  • Analog block-level functional modeling

Day 2 — Block-Level Mixed-Signal Modeling

  • Review of Verilog
  • Review of Verilog-AMS
  • Mixed-signal block-level functional modeling
  • Mixed-signal netlists
  • Assertions

Day 3 — Block Level Analog Verification

  • Block-level verification strategy
  • Writing self-checking regression tests
  • Techniques for testing common mixed-signal blocks
  • Overcoming analog verification problems

Day 4 — System Level Analog Verification

  • System-level verification strategy
  • Verilog modeling of analog systems
  • Verifying the top-level model
  • Chip-level verification strategy
  • Verification review

Day 5 (optional) — Taking Analog Verification Into Production

  • Generating models with Models-in-Minutes
  • Generating testbenches with Models-in-Minutes
  • Verification from the Linux command line
  • Best analog verification practices in a production setting

Days 1 & 2 are an in-depth refresher on Verilog, Verilog-A and Verilog-AMS, with an emphasis on best practices. Day 3 is often overlooked, but it is perhaps the most important day. It is where we teach you to create automated regression tests that thoroughly exercise and verify mixed-signal designs. It is a very unique aspect of this class. On day 4 we cover chip/analog subsystem level connectivity, function checking, and how to write Verilog models for chip level verification, with a focus on not only how to make them very efficient, but also how to assure that they are functionally equivalent to the circuit.

The class is structured to alternate between lecture and labs, with a large percentage of the class dedicated to rather open ended labs. In this way, everyone is challenged and learns a great deal, regardless of their experience level. People that are new to Verilog-AMS often just use the labs to gain experience with the language and simulator. Those with a lot of experience with the language challenge themselves more with the verification aspects.

Modeling Basics for Analog/Mixed-Signal/RF Design and Verification (3 days)

For good reasons, modeling has become an integral part of analog design, especially as design complexity increases. Most designers have never taken a deep class in Verilog-A where what the model is doing is tied with the underlying simulator. As a result, designers often write models that simulate slowly, fail to produce desired results, and have convergence and time step issues. This class teaches the Verilog-A and Verilog-AMS languages with an emphasis on creating well formulated models that run efficiently and do not suffer from convergence or simulation issues. The goal of this class is to give a solid foundation to engineers new to modeling and to improve the modeling skills of designers already familiar with modeling.

Target Audience

The class is intended for anyone who would benefit from having a solid foundation in Verilog-A and Verilog-AMS. These include: Analog/Mixed-Signal/RF Designers, Novice Analog or Mixed-Signal Verification Engineers, EDA Engineers.


Ken Kundert and Henry Chang

Learning Objectives

  • Learn the fundamentals of the Verilog-A and Verilog-AMS languages
  • Learn enough Verilog (digital) to write good Verilog-AMS for the digital portions of the model
  • Learn the fundamentals of what makes a good model
  • Learn how what you write ties in with the simulator in terms of accuracy, robustness, and efficiency
  • Learn best practices of modeling
  • Uses challenging lab exercises to reinforce learning
  • Gain a solid foundation of modeling to get more out of the Analog Design Verification class
  • Be able to get questions around analog modeling answered; questions which may be beyond the scope of the class

Course Contents

  • Introduction to Modeling
  • Device Modeling with Verilog-A
  • Functional Modeling with Verilog-A
  • Verilog-A Best Practices
  • Modeling with Verilog
  • Modeling with Verilog-AMS
  • Modeling with Verilog-AMS wreals
  • Power Domains and Connect Modules
  • Introduction to testbench writing

Effective Use of Circuit Simulation for Analog/Mixed-Signal/RF Designs (3 days)

The emphasis of this class is on increasing the designer's effectiveness when using a simulator by giving them a basic understanding of how the simulator works so that they can better control it and resolve problems that come up and by exposing them to many simulation best practices. From the class, the designer should be able to better discern when simulation results are good predictors of actual performance and when simulators have limitations. Throughout the class, different circuit examples from different design domains are given. The labs focus on setting up testbenches to reinforce the topics being taught.

Target Audience

The class is intended for analog/mixed-signal/RF designers, and analog verification engineers.


Ken Kundert

Course Contents

  • When to simulate
  • How the simulator works
  • Formulating and solving the equations
  • Tolerances
  • DC analysis
  • Small-signal analysis (including AC, XF, noise, stability/loop gain, etc.)
  • Transient analysis
  • Fourier analysis
  • Corner Analysis and Monte Carlo Simulation
  • Introduction to RF simulation

Introduction to Analog Verification (2 days)

This two day course provides an in depth introduction to the verification of complex analog, RF, and mixed-signal integrated circuits. It combines lecture with labs to illustrate the concepts in analog verification. You will learn the principles of analog verification and the basics so that you can effectively interact with analog verification engineers such as working with them to develop the verification plan, understanding analog verification terminology, and gaining some ability to read the models and regression tests they create.

Target Audience

Those who want to get a solid introduction to analog verification- design managers, design leads, digital verification engineers, analog designers, CAD engineers; anyone who needs to work with analog verification engineers; and those considering becoming analog verification engineer


Ken Kundert and Henry Chang.


Students should have some knowledge of analog circuits. Knowing how to use the Cadence design environment is helpful. Experience in modeling with Verilog, Verilog-A, and Verilog-AMS is a plus, but it is not necessary. The better prepared you are, the more you will get from the class.

Course Contents

Day 1 — Introduction and Modeling

  • Introduction to Analog Verification
  • Getting started with the Modeling Languages
  • Mixed-Signal Block Level Functional Modeling

Day 2 — Regression Testing

  • Verification Planning
  • Block level self checking regression tests
  • System-level verification

Day 1 provides an introduction to analog verification. This is followed by a lecture on the subset of Verilog, Verilog-A, and Verilog-AMS that we commonly use in Analog Verification. This lecture on the behavioral modeling languages assumes that you have no prior experience with any of these languages. However, this lecture will likely seem fast paced if you, indeed, have no background. This is followed by a talk on how an AV engineer writes models for functional verification. Our goal is to provide sufficient information so that at the end of the class you are able to read, maybe modify slightly, a model or regression test that an AV engineer, trained by us, has written.

Day 2 continues the introduction to analog verification by discussing verification planning. We give a fairly comprehensive lecture on this subject, because it is in verification planning that there is a great deal of active engagement between the members of the design team and the analog verification engineers. Developing a good verification plan up front is key to ensuring that you verify what you want, that it is done in an efficient manner, and that the effort can be completed. We then discuss block level self checking regression testing and finally discuss how to verify at the chip and system level. Again, the emphasis here is to give you an understanding of what the AV engineer is trying to accomplish. In this way, you can better interact with the AV engineers, but also, by understanding what the AV engineer will be verifying, you can leverage their work potentially saving you effort as you work on the design.

Unlike the four day class, the majority of the time is spent in lecture. However, we do provide 3 labs — one on using block level functional models, one on running block level regression tests, and one at running system level simulations.

Classes are held worldwide at your facilities. Please feel free to contact us if you are interested in a class.

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