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We tried the methodology once and we are convinced.  We are now converting all new designs to this methodology.  There is no other way.

The approach to Yosemite's Half Dome

A New Approach Is Needed

Designer’s Guide Consulting is a unique consulting firm that specializes in helping companies transform their design process to one that employs a rigorous analog verification methodology. This methodology is much like the one used by digital verification groups. Once adopted, design teams are typically able to fully verify the functionality of their designs to the transistor level every night using pass/fail regression tests. Not only does this methodology fully verify the design, but it also produces a fully verified high-level Verilog or Verilog-AMS model of the design and confirms that both the design and the model are consistent with the stated functional specifications. And while the primary concern of the methodology is functional verification, it also supports performance verification by dramatically accelerating the simulation of non-critical blocks.

A Proven Methodology

The methodology taught by Designer’s Guide Consulting has been used with great success by a handful of companies, both large and small. Consider some examples. Analog verification was recently applied to the analog portion of a large mixed-signal SoC. The verification process entered its final phase during tape out. At this point the designers believed the design to be complete and ready to go. However, a half dozen functional errors were hiding in the design, all of which were exposed using the methodology. These errors were all centered on the part of the circuit that had the most difficult performance requirements and was the most difficult to simulate. The design team was so focused on meeting the performance requirements that they never got around to verifying the basic functional requirements; a very common source of errors. In another case the errors were hiding in the digital circuitry that processed the signals produced by the analog section. Here the fully verified Verilog model of the analog section allowed the digital RTL code to be tested with the analog portion of the design, which exposed these errors.

How Can I Learn More About The Approach?

How Can I Benefit From This Approach?

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