Ruby Lake, Ansel Adams Wilderness

We offer training classes that are both demanding and rewarding. They are intended to get you started in analog verification.

Analog Verification

This four day course provides participants with the tools they need to take on the task of verifying complex analog, RF, and mixed-signal integrated circuits. It combines lecture with a substantial amount of time in the lab to teach the overall analog verification process. You will learn how to develop a verification plan, functional models of analog blocks, regression tests for those models, and a fully verified Verilog model for the entire analog portion of the design for use in chip-level verification.

Target Audience
The class is intended for anyone who would benefit from a working knowledge of analog verification or from improving their skills with Verilog-A/MS. These include: analog verification engineers, analog designers, and digital verification engineers and CAD engineers who meet the prerequisites.

Instructors
Ken Kundert and Henry Chang.

Prerequisites
Students should have a working knowledge of Verilog-A, analog circuits and their design, and the Cadence design environment. It is also helpful to have gone through Verilog-AMS training. The better prepared you are, the more you will get from the class.

Course Contents
Day 1 – Introduction and Block-Level Analog Modeling

• Introduction to analog verification
  
• Verification planning
  
• Review of Verilog-A
  
• Analog block-level functional modeling
  

Day 2 – Block-Level Mixed-Signal Modeling

• Review of Verilog
  
• Review of Verilog-AMS
  
• Mixed-signal block-level functional modeling
  
• Mixed-signal netlists
  
• Assertions
  

Day 3 – Block Level Analog Verification

• Block-level verification strategy
  
• Writing self-checking regression tests
  
• Techniques for testing common mixed-signal blocks
  
• Overcoming analog verification problems
  

Day 4 – System Level Analog Verification and Top-Down Design

• System-level verification strategy
  
• Verilog modeling of analog systems
  
• Verifying the top-level model
  
• Chip-level verification strategy
  
• Verification review
  

Days 1 & 2 are an in-depth refresher on Verilog, Verilog-A and Verilog-AMS, with an emphasis on best practices. Day 3 is often overlooked, but it is perhaps the most important day. It is where we teach you to create automated regression tests that throughly exercise and verify mixed-signal designs. It is a very unique aspect of this class. On day 4 we cover chip/analog subsystem level connectivity, function checking, and how to write Verilog models for chip level verification, with a focus on not only how to make them very efficient, but also how to assure that they are functionally equivalent to the circuit.

The class is structured to alternate between lecture and labs, with a large percentage of the class dedicated to rather open ended labs. In this way, everyone is challenged and learns a great deal, regardless of their experience level. People that are new to Verilog-AMS often just use the labs to gain experience with the language and simulator. Those with a lot of experience with the language challenge themselves more with the verification aspects.

Cancellation
In the event that you have to cancel, half of the class fee will be refunded if we receive the cancellation notice 4 weeks prior to the start of the class.  Within 4 weeks of the start of the class, no refunds will be given.

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